The negative edge triggered flip-flop of claim 1 wherein said pulse generator circuit includes:Ī multiplexor circuit multiplexing said data input signals with said at least one control signal wherein said one of said at least one control signals results in the state of said selected data input signal being output as an evaluation signal, andĪn output pulse generator generating an output pulse when said evaluation signal has a predetermined digital value.Ħ.
The negative edge triggered flip-flop of claim 3 wherein said header circuit generates said at least one control signal by performing a NOR operation between said select-enable signal and said clock signal.ĥ.
The negative edge triggered flip-flop of claim 2 wherein said header circuit combines said clock signal with one of said select input signals by performing a NAND operation to generate said select-enable signal.Ĥ. The negative edge triggered flip-flop of claim 1 wherein said header circuit integrates said clock signal with said select input signals by combining said clock signal with one of said select input signals to generate a select-enable signal, then combining said select-enable signal with said clock signal to generate said at least one control signal.ģ. A negative edge triggered flip-flop, comprising:Ī first set of nodes receiving data input signals Ī second set of nodes receiving select input signals for selecting one data input signal of said data input signals as a selected data input signal Ī clock node receiving a clock signal having a positive edge and a negative edge Ī header circuit connected to said second set of nodes and to said clock node, said header circuit integrating said clock signal with said select input signals to generate at least one control signal andĪ pulse generator circuit connected to said first set of nodes, said header circuit and said output node, said pulse generator circuit generating an output pulse on said output node in response to said at least one control signal and said selected data input signal, such that said output pulse is generated in response to said negative edge of said clock signal.Ģ.
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